The DS1135 treats time as a component: where digital designs once tuned delays with gate chains, RC networks or board-trace lengths, this all-silicon delay line packages three independent, factory-trimmed delays in one 8-pin device. Signal in, the same signal out - 25 ns later per channel in this -25 grade. DS1135Z-25+T&R is the lead-free SOIC-8 (150 mil) on tape and reel; the family spans 6 to 30 ns per step, and the DS1135L sibling serves 3.3 V systems.

What makes a silicon delay line worth a part number is the accuracy guarantee: ±1.5 ns initial tolerance for the 25 ns grade at 25°C/5 V, held to ±1.5 ns over 0°C to +70°C and ±2 ns across the full -40°C to +85°C industrial range. A chain of logic gates drifts with process, voltage and temperature; the DS1135's trimmed timing circuit does not. Equally important, delay accuracy applies to both edges, so a clock's duty cycle and a pulse's width pass through unchanged.

Interfacing is plain digital: TTL/LS-TTL and CMOS-compatible inputs (VIH 2.2 V / VIL 0.8 V), non-inverting buffered outputs that each drive up to 10 LS loads (IOL 12 mA), one +5 V supply at 35 mA max. Three channels in one package align three signal paths - clock to two data groups, three memory strobes, or cascaded for longer delays - replacing the older DS1013/DS1035 directly at higher speed grades.

Note: Values are taken from the Maxim DS1135 datasheet. Confirm every parameter against the latest official documentation before committing a design.

DS1135Z-25+T&R comes in the 8-lead, 150 mil SOIC (Maxim outline 21-0041, JEDEC MS-012 class, 1.27 mm pitch) - the "Z" in the part number. The "+" marks the lead-free finish and "T&R" the tape-and-reel packing; the device is vapor-phase, IR and wave solderable. Layout is simple logic practice: a 0.1 µF bypass at VCC, and remember that output trace capacitance adds to the delay - keep delayed-clock runs short and consistently loaded when channel-to-channel alignment matters. Package dimensions and pin-1 orientation are shown below.

📄 Full specifications are detailed in the official Maxim DS1135 datasheet.

The 8-lead SOIC pairs the three inputs on the left with their outputs mirrored on the right:

• Pin 1 - IN1: Delay line 1 input (TTL/CMOS compatible).
• Pin 2 - IN2: Delay line 2 input.
• Pin 3 - IN3: Delay line 3 input.
• Pin 4 - GND: Ground.
• Pin 5 - OUT3: Delay line 3 output - IN3 delayed 25 ns, non-inverted.
• Pin 6 - OUT2: Delay line 2 output.
• Pin 7 - OUT1: Delay line 1 output.
• Pin 8 - VCC: +5 V supply; bypass with 0.1 µF at the pin.

Refer to the package drawing below for the physical pin numbering of the SOIC-8.

The parts below are related silicon delay lines available in our catalog. They are not drop-in replacements; verify channel count, delay value/taps, supply voltage and package before substituting.

Selection Tips: Stay with the DS1135 for three fixed, matched delays on 5 V - pick the grade (6-30 ns) that fits the budget. The DS1135L serves 3.3 V rails; the DS1100/DS1110 give one signal multiple taps; the DS1124 makes the delay programmable; the DS1035 is the legacy part this one was designed to replace.

Dallas Semiconductor built the silicon delay line category - timing sold as a trimmed, guaranteed component - and Maxim Integrated (which acquired Dallas in 2001, and itself became part of Analog Devices, Inc. in 2021) carried the DS-series timing parts forward. The DS1135 is the high-speed 3-in-1 member, the recommended replacement for the earlier DS1013/DS1035.

The combined ADI/Maxim catalog keeps the DS1135 documented with full datasheet characterization - delay tables per grade, tolerance over temperature and voltage, and edge-accuracy guarantees - the numbers a timing budget is signed off against.