The MAX5180/MAX5183 from Maxim Integrated (now part of Analog Devices) are dual, 10-bit, simultaneous-update digital-to-analog converters designed for the analog signal reconstruction that communications systems demand - low distortion, low power, two channels that move together. The MAX5183 is the voltage-output member of the pair: it carries on-chip precision resistors that turn the core current output into a differential voltage on OUT_P/OUT_N, where the MAX5180 leaves the output as current. MAX5183BEEI+ is the RoHS ("+") option in the 28-pin QSOP.

The signal path is built for I and Q. Both DACs share a single 10-bit parallel bus (D0-D9) clocked by CLK, and they update simultaneously - the reason gain and phase between the two channels are held to ±0.5 %FSR and ±0.2°, the matching a quadrature modulator lives or dies on. Reconstruction quality is set by a 70 dB spurious-free dynamic range (f_OUT = 2.2 MHz), -60 dB DAC-to-DAC isolation and the internal 1.2 V low-noise bandgap reference, which can be overridden through REFR/REFO when a system reference is preferred.

Power is managed in three states rather than one. DACEN and PD together select normal operation, a fast-wake standby, or a deep full shutdown - so an I/Q transmitter can drop the converters between bursts and bring them back quickly. The part runs from a single 2.7 V to 3.3 V supply (separate AV_DD/DV_DD and AGND/DGND for clean analog-digital separation), and the whole device fits the compact 28-pin QSOP over the -40 °C to +85 °C extended range.

Note: Values are taken from the Maxim MAX5180/MAX5183 datasheet. Confirm every parameter against the latest official documentation before committing a design.

MAX5183BEEI+ ships in the 28-pin QSOP (Quarter-Size Outline Package, outline 21-0055) - a 0.150-inch-wide body on 0.025-inch pin pitch that holds 28 leads in roughly the footprint of a 16-lead SOIC, which is why a dual converter with a full 10-bit bus fits where board space is tight. Because the two channels share one package, the analog and digital domains must stay apart on the board: bypass AV_DD and DV_DD at their own pins, keep the OUT1/OUT2 differential pairs symmetric and away from the D0-D9 bus and CLK, and bypass the CREF1/CREF2 and REFO reference pins close in. The dimensional drawing below gives the full mechanical detail.

The 28-pin QSOP groups the two analog channels on the outer ends and the digital bus along one side (per the MAX5180/MAX5183 datasheet):

• Pins 2, 3 - OUT1P, OUT1N: DAC1 differential analog output (voltage output on MAX5183).
• Pins 27, 26 - OUT2P, OUT2N: DAC2 differential analog output (voltage output on MAX5183).
• Pins 1, 28 - CREF1, CREF2: Reference bias bypass for DAC1 and DAC2.
• Pin 24 - REFR: Reference input. Pin 25 - REFO: Reference output (internal 1.2 V bandgap).
• Pin 11 - REN̅: Active-low reference enable; tie to DGND to activate the on-chip 1.2 V reference.
• Pins 12-21 - D0...D9: 10-bit parallel data input, D0 = LSB, D9 = MSB.
• Pin 9 - CLK: Clock input. Pin 8 - CS̅: Active-low chip select.
• Pin 6 - DACEN, Pin 7 - PD: DAC-enable and power-down select - together choose normal, standby or shutdown.
• Pins 5, 22 - AV_DD, DV_DD: Analog and digital +2.7 V to +3.3 V supplies. Pins 4, 23 - AGND, DGND: Analog and digital grounds.
• Pin 10 - N.C.: No connect - do not connect to this pin.

The closest options are the current-output twin and the rest of Maxim's dual/communications DAC line. Match output type, resolution and interface to your signal chain before substituting.

Selection Tips: Stay with the MAX5183 for a ready differential voltage output; choose the MAX5180 when your modulator wants the raw current output. Step to the MAX5170/MAX5176 when one channel and higher resolution matter more than the dual, 40 MHz I/Q pairing. Confirm the parallel-bus timing budget against your DSP before locking the layout.

Maxim Integrated, now part of Analog Devices, Inc. (ADI), built the MAX5180/MAX5183 for the demanding corner of data conversion where two channels must track each other through a 40 MHz reconstruction - the I/Q transmit path of a communications system, where channel match, not just per-channel linearity, sets the achievable image rejection.

ADI maintains the datasheet, dynamic-performance plots (SFDR, THD, channel isolation) and the layout and reference-bypass guidance for the family - the documentation that turns the ±0.2° phase match on the data sheet into image rejection on the bench.