The SN74LVC1G125-Q1 is a single 3-state bus buffer: the output follows the input (Y = A) when the active-low output-enable is asserted and goes high-impedance otherwise, so the device can drive or release a shared line. This order option packs that function into the DRY (SON) outline — one of the smallest standard packages able to carry a complete single gate — for designs where every square millimetre counts.

Despite the size, nothing is given up electrically. The inputs are 5.5 V-tolerant and the output swings to V_CC, so the part still does clean down-translation (read a 5 V signal, present it at a 3.3 V or 1.8 V rail) with a strong ±24 mA drive. The I_off partial-power-down circuit still supports live insertion and back-drive protection, and the “-Q1” automotive qualification (−40 °C to +125 °C) still applies.

The DRY package is a 6-pin SON: the five buffer signals plus one no-connect (NC) pin. At about 10 µA quiescent it suits battery-powered wearables, hearables, medical sensors and other space- and power-constrained boards that still need a clean, isolatable bus interface.

Note: Values are from the Texas Instruments SN74LVC1G125-Q1 data sheet (SGES002E). Confirm every parameter against the latest data sheet before committing a design.

This order option uses the DRY package — a 6-pin SON (leadless), about 1.45 mm × 1.00 mm with a 0.55 mm maximum height and 0.5 mm pitch. It is one of the smallest outlines available for a complete single-gate buffer, trading the easy-to-inspect leads of SC-70/SOT-23 for minimum board area and z-height. The same die is also offered in DCK (SC-70) and DBV (SOT-23) for less space-critical designs.

Use the dimensioned drawing below to build the SON land pattern, paste stencil and keep-out — bottom-terminated parts are sensitive to footprint and reflow.

The DRY package adds one no-connect to the five buffer signals (top view):

• Pin 1 – OE (Output Enable, active-low): low enables Y = A; high forces Hi-Z. 5.5 V-tolerant.
• Pin 2 – A (Input): data input; 5.5 V-tolerant.
• Pin 3 – GND: Ground (0 V) reference.
• Pin 4 – Y (Output): 3-state output; ±24 mA at 3.3 V or Hi-Z.
• Pin 5 – NC: No internal connection; leave floating (do not use as a tie-point or via).
• Pin 6 – V_CC: Supply, 1.65 V to 5.5 V; decouple with a local 0.1 µF capacitor.

The same buffer in larger packages, plus family alternatives. The first row is the SC-70 option of this device; the SN74LVC1G126 is the active-high counterpart. Confirm package, family and enable polarity before substituting.

Logic Family Comparison

Texas Instruments (TI, NASDAQ: TXN), of Dallas, Texas, offers its single-gate logic in a wide range of packages from SOT-23 down to leadless SON/X2SON, so designers can keep the same proven LVC die while optimising for board area. The “-Q1” variants are AEC-Q100 qualified.

The governing document is the SN74LVC1G125-Q1 data sheet (SGES002E), which defines the electrical limits, the I_off behaviour and the DRY/DCK/DBV package outlines. InFortune Electronics supplies the device under code 1P1G125QDRYRQ1 and provides sourcing and technical support.