The SN74LVC1G126-Q1 is a single 3-state bus buffer with an active-HIGH output enable: the output follows the input (Y = A) when OE is high and switches to high-impedance when OE is low. This order option delivers that function in the DRY (SON) package — a 6-pin leadless outline among the smallest that can carry a complete single gate — for area-critical boards that still need clean, gated bus access with high-true enable logic.

Nothing is sacrificed electrically. Inputs are 5.5 V-tolerant and the output swings to V_CC, so the part performs clean down-translation with a strong ±24 mA drive, and the I_off partial-power-down circuit still supports live insertion and back-drive protection. The “-Q1” automotive qualification (−40 °C to +125 °C) applies, at about 10 µA quiescent.

The active-high enable is the only logical difference from the SN74LVC1G125 (active-low). Choosing the '126 lets a naturally high-true grant or select signal enable the buffer directly, without an inverter in the control path — useful when board area is already tight.

Note: Values are from the Texas Instruments SN74LVC1G126-Q1 data sheet (SCES467D). Confirm every parameter against the latest data sheet before committing a design.

This order option uses the DRY package — a 6-pin SON (leadless), about 1.45 mm × 1.00 mm with a 0.55 mm maximum height. It trades the easy-to-inspect leads of SOT-23 for minimum board area and z-height. The same active-high buffer die is also offered in DBV (SOT-23) for less space-critical designs.

Use the dimensioned drawing below to build the SON land pattern and stencil — bottom-terminated parts are sensitive to footprint and reflow.

The DRY package adds one no-connect to the five buffer signals (top view):

• Pin 1 – OE (Output Enable, active-high): high enables Y = A; low forces Hi-Z. 5.5 V-tolerant.
• Pin 2 – A (Input): data input; 5.5 V-tolerant.
• Pin 3 – GND: Ground (0 V) reference.
• Pin 4 – Y (Output): 3-state output; ±24 mA at 3.3 V or Hi-Z.
• Pin 5 – NC: No internal connection; leave floating.
• Pin 6 – V_CC: Supply, 1.65 V to 5.5 V; decouple with a local 0.1 µF capacitor.

The same active-high buffer in SOT-23, plus the active-low counterpart and family options. Confirm package, family and enable polarity before substituting.

Logic Family Comparison

Texas Instruments (TI, NASDAQ: TXN), of Dallas, Texas, offers its single 3-state buffers in both enable polarities and a wide range of packages from SOT-23 down to leadless SON, letting designers match enable sense and board area while keeping the same proven LVC die. The “-Q1” variants are AEC-Q100 qualified.

The governing document is the SN74LVC1G126-Q1 data sheet (SCES467D), defining the 3-state behaviour, I_off and the DBV/DRY packages. InFortune Electronics supplies the device under code 1P1G126QDRYRQ1 and provides sourcing and technical support.